1. Field of the Invention
The present invention relates to a wafer burn-in test and a wafer test circuit for a semiconductor memory device using a probe pad for contact, and in particular to a wafer burn-in test and a wafer test circuit which can cut down packaging expenses and improve F/T yield by performing a wafer burn-in test by using a pad for contact in a probe test of a wafer state.
2. Description of the Background Art
In general, a screening test is performed to identify a DRAM having a defect at an early stage. The screening test mostly employs a burn-in test mode (a high temperature high voltage operation test). The burn-in test operation exposes a potential defect in the DRAM in a short time by operating the DRAM in the worst conditions such as at a high temperature and a high voltage. In the burn-in test operation, an appropriate stress voltage, especially an accelerating stress voltage, is applied to the respective units of the chip to detect the defect.
The burn-in test operation is used not only for the DRAM but also for the other semiconductor memory devices. An internal power circuit for generating an internal power voltage Vint to the DRAM adjusts the internal voltage so that an internal circuit cannot receive an excessive stress voltage in the burn-in test operation, and thus applies only a stress voltage for screening thereto.
Generally, actual contact with the semiconductor memory device using a probe pad for contact is performed after a probe test of a wafer state and before packaging. Accordingly, when an inferior chip is not sufficiently screened in the probe test, if a defect occurs after packaging, the chip cannot be repaired. In order to solve the foregoing problem, the wafer burn-in test is executed in the wafer state before packaging.
FIG. 1 is a block diagram illustrating a conventional wafer burn-in test circuit including a first probe pad unit 1 for contact, a second probe pad unit 2 for contact, a first buffer unit 3, a second buffer unit 4, a decoder unit 5, a data multiplexer unit 6, a test mode block unit 7 and an array control unit 8.
The first buffer unit 3 converts a signal BOP0IN inputted through the first probe pad unit 1 for contact into a CMOS level, and the second buffer unit 4 converts a signal BOP1IN inputted through the second probe pad unit 2 for contact into a CMOS level.
The decoder unit 5 receives the signals BOP0 and BOP1 from the first and second buffer units 3 and 4, and generates a control signal BPX less than 0:1 greater than . The data multiplexer unit 6 inputs/outputs a desired data bit based on the control signal BPX less than 0:1 greater than  from the decoder unit 5.
The test mode block unit 7 generates a control signal TBIN less than 0:1 greater than  in the wafer burn-in test mode. The array control unit 8 controls bit lines, word lines and plate lines making up an access transistor (not shown) of a memory cell based on the control signal TBIN less than 0:1 greater than  from the test mode block unit 7, thereby applying a stress voltage to the cell, bit line and storage node.
FIG. 2 is a circuit diagram illustrating the first buffer unit 3 of FIG. 1. The first buffer unit 3 includes: a PMOS transistor MP1 for transmitting a power voltage VDD to a node Nd1 based on a power-up signal PUPB; a PMOS transistor MP2 for transmitting the power voltage VDD to the node Nd1 based on an initialization signal IDL; a PMOS transistor MP3 for transmitting the power voltage VDD to the node Nd1 based on a ground voltage VSS; a PMOS transistor MP4 for transmitting the signal of the node Nd1 to a node Nd2 transmitting the signal BOP0IN from the first probe pad unit 1 based on the ground voltage VSS; an inverter IV2 for receiving the signal of the node Nd2, and outputting an inverted signal to a node Nd3; a PMOS transistor MP5 for transmitting the power voltage VDD to the node Nd2 based on the signal of the node Nd3; and an inverter IV3 for receiving the signal of the node Nd3, and outputting an inverted signal BOP0.
When the power-up signal PUPB has a high state, the power voltage VDD is supplied to the node Nd1 through the PMOS transistors MP1 and MP3, and the signal of the node Nd1 is transmitted to the node Nd2 through the PMOS transistor MP4. Therefore, the signal BOP0IN of the node Nd2 has a high state during the power-up operation, and the output signal BOP0 has a high state. That is, the first buffer unit 3 maintains the initial state during non-contact by the first probe pad unit 1.
The second buffer unit 4 of FIG. 1 has the same constitution and operation as the first buffer unit 3 of FIG. 2. Accordingly, the input signal BOP1IN of the second buffer unit 4 has a high state during the power-up operation, and the output signal BOP1 has a high state. Identically, the second buffer unit 4 serves to maintain the initial state during non-contact by the second probe pad unit 2.
FIG. 3 is a circuit diagram illustrating the decoder unit 5 of FIG. 1. The decoder unit 5 includes: an inverter IV10 for receiving the output signal BOP0 from the first buffer unit 3, and outputting an inverted signal; an inverter IV20 for receiving the output signal BOP1 from the second buffer unit 4, and outputting an inverted signal; an inverter IV30 for receiving the output signal from the inverter IV20, and outputting an inverted signal; a NAND gate ND for receiving the output signals from the inverters IV10 and IV20; inverters IV50 and IV60 connected in series between an output node Nd30 of the NAND gate ND and a node Nd40 transmitting a control signal BPX8; a NOR gate NR for receiving the output signal from the NAND gate ND and the output signal from the inverter IV20, and outputting a control signal BPX4; and an inverter IV40 connected between an output node Nd20 of the inverter IV30 and a node Nd50 transmitting a control signal BPX16.
When the input signal BOP0 from the first buffer unit 3 and the input signal BOP1 from the second buffer unit 4 have a low state, the output signal BPX8 has a high state, the output signal BPX4 has a low state, and the output signal BPX16 has a high state. When the input signal BOP0 and the input signal BOP1 have a high state, the output signal BPX8 has a high state, the output signal BPX4 has a low state, and the output signal BPX16 has a low state. When the input signal BOP0 has a low state and the input signal BOP1 has a high state, the output signal BPX8, the output signal BPX4 and the output signal BPX16 have a low state. When the input signal BOP0 has a high state and the input signal BOP1 has a low state, the output signal BPX8 has a high state, the output signal BPX4 has a low state, and the output signal BPX16 has a high state.
The data multiplexer unit 6 controls input/output of a desired data bit based on the output signal BPX less than 0:1 greater than  from the decoder unit 5.
However, the conventional wafer burn-in test circuit has a disadvantage in that, although the number of prober pins for the wafer burn-in test is reduced in using the probe pad for the wafer burn-in test, the chip area is increased due to the probe pad. Moreover, since address information is required for the wafer burn-in test in the test mode using an address key, the number of the prober pins for the test is increased, thereby increasing the prober production cost and the setting time before the test.
Accordingly, it is an object of the present invention to provide a wafer burn-in test and a wafer test circuit which can cut down packaging expenses, improve F/T yield and reduce the production cost, by screening an inferior chip before packaging by executing a wafer burn-in test with a fuse and a probe pad for contact prior to the contact.
In order to achieve the above-described object of the invention, there is provided a wafer test circuit including: a buffer unit for initializing an input signal inputted through a probe pad unit having a floating state during non-contact before blowing a wafer, converting the signal into a CMOS level, and outputting the converted signal; a fuse unit for generating a first control signal for selecting a signal generation path for the test operation of a wafer state before blowing the wafer, and a signal generation path for the operation of a bit line after blowing the wafer; a multiplexer unit for receiving the first control signal from the fuse unit and the output signal from the buffer unit, generating a second control signal for the wafer test operation before blowing the wafer, and generating a third control signal for the operation of the bit line after blowing the wafer based on the first control signal; and a decoder unit for receiving the output signal from the multiplexer unit, and generating a decoded signal.
In another aspect of the present invention, a wafer test circuit includes: a first buffer unit for initializing an input signal inputted through a probe pad unit having a floating state during non-contact before blowing a wafer, converting the signal into a CMOS level, and outputting the converted signal; a fuse unit for generating a first control signal for selecting a signal generation path for the test operation of a wafer state before blowing the wafer, and a signal generation path for the operation of a bit line after blowing the wafer; a multiplexer unit for receiving the first control signal from the fuse unit and the output signal from the first buffer unit, generating a second control signal for the wafer test operation before blowing the wafer, and generating a third control signal for the operation of the bit line after blowing the wafer based on the first control signal; and a second buffer unit for receiving the output signal from the multiplexer unit, and generating a buffered signal.
In still another aspect of the present invention, a wafer burn-in test circuit includes: first and second probe pad units having a floating state before blowing a wafer; a first buffer unit for initializing a signal from the first probe pad unit in a power-up operation based on a power-up signal, converting the signal into a CMOS level, and outputting the converted signal; a second buffer unit for initializing a signal from the second probe pad unit during the power-up operation based on the power-up signal, converting the signal into a CMOS level, and outputting the converted signal; a fuse unit for generating a first control signal for selecting a signal generation path for a burn-in test operation of a wafer state before blowing the wafer, and a signal generation path for the operation of a bit line after blowing the wafer; a decoder and multiplexer unit for receiving the first control signal from the fuse unit and the output signals from the first and second buffer units, generating a second control signal for the wafer test operation before blowing the wafer, and generating a third control signal for the operation of the bit line after blowing the wafer based on the first control signal; a test mode block unit for generating a fourth control signal in the wafer burn-in test mode based on the second control signal from the decoder and multiplexer unit; an array control unit for controlling bit lines, word lines and plate lines making up an access transistor of a memory cell based on the fourth control signal from the test mode block unit, and applying a stress to the cell, bit line and storage node; and a data multiplexer unit for controlling input/output of a desired data bit based on the third control signal from the decoder and multiplexer unit.